On Sat, 26 May 2012, lloyd wilson wrote: > Date: Sat, 26 May 2012 12:20:38 -0400 > From: lloyd wilson <llwilso...@rochester.rr.com> > Reply-To: "Enhanced Machine Controller (EMC)" > <emc-users@lists.sourceforge.net> > To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net> > Subject: Re: [Emc-users] spindle tachometer strangeness > > negativity should work, understanding would be more satisfying. > > -ldw >
The counter mode counts up or down depending on the state of the B encoder input at the FPGA (count up for high, down for low). You can verify the B encoder input state by reading the GPIO bit that maps to the B encoder input of interest. complicating factors: 1. The up/down mode is determined by the state at the FPGA pin. Most input conditioning daughterboards invert the encoder signals so the external state will be opposite of the FPGA pin state. 2. Some configurations do not have B inputs as they are just used for counting applications. In this case the counter will always count down (since unconnected inputs are terminated in a 0 state internally in the FPGA) Peter Wallace ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
