On 19.03.2016 20:20, Nicklas Karlsson wrote: >> Hi Gene! >> >> On 19.03.2016 19:24, Gene Heskett wrote: >>> [...] >>> >>> In 1978 I needed to generate an academy countdown leader, 9.9 to 1.9 >>> seconds until 1st video, on an RCA 1802 processor, which has built in >>> dma. This thing ran at the smoking clock speed of 1.79 Mhz, but a full >>> processor cycle was 8 clocks. Said another way its speed was 223,750 >>> instructions per second. And I was able to do it on 6 DMA cycles per >>> vertical field, using previously composed data, generating characters >>> big enough they could be read on a 5" monitor from 20' away by operators >>> with reasonably good eyesight. >>> >>> It worked without a hitch even at that slow a machine cycle because any >>> time a DMARQ went down, the next machine cycle serviced it. With >>> more "modern" cpu's, that is not always the case. Some treat dma as >>> needing a full context dump to the stack first. Both RCA and TI got it >>> right the first time, but TI did have to reload the program counter >>> pointer which took a machine cycle. RCA did not as with 16 ea 16 bit >>> registers, they just assigned one of them to be the dma access pointer. >>> >>> IMO you can smell time wasting stacking of the processor state and its >>> recovery when the dma had been serviced 500 yards upwind of a dry lot >>> operation on a below zero February morning. For those of you not raised >>> on a farm, I'll just say its legendary and you'll never forget it. >>> >>> Modern disclaimer: I have no clue what sort of priority is given DMA by >>> todays crop of CPU's. Sure they've gotten faster, but are they better? >> >> It's a bit off-topic, but anyways: DMA controllers in recent >> microcontrollers can be quite complex beasts, far from a simple >> incrementing pointer for copy operations. Some use dynamic descriptors >> in memory, which hold the DMA configuration. One of the config options >> in each descriptor holds the address of the next descriptor. With this, >> you can generate "any number" of such descriptors and then start the DMA >> with the address of the first and it will (optionally looping forever) >> copy N words from here to there, then M words from foo to bar, followed >> by K words, etc. without any CPU intervention at all. Usually it is also >> possible to trigger the DMA using a hardware timer, so you could get >> away without any interrupt for this transfers at all. But of course the >> DMA controller has to access the bus as well, so if the CPU is doing >> some heavy memory access on its own, the DMA may be slowed down quite much. > > Are you sure CPU slow down DMA and not the opposite?
Depends on the priorities, the DMA may be configurable to get higher priority than the CPU. But I'd suspect the "CPU comes first" approach to be more common, as the CPU should usually be busy with not so memory intensive tasks, so performance will increase if it only has to take the bus every once in a while and continue immediately with its work, while the DMA is using all the rest of the bandwidth. Bye, Philipp
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