On Tuesday 16 May 2017 15:56:24 Gene Heskett wrote: > On Tuesday 16 May 2017 15:03:00 Bertho Stultiens wrote: > > On 05/16/2017 08:33 PM, Peter C. Wallace wrote: > > > 50 MHz will work if everything is terminated correctly and if the > > > RSPI timing is correct. (It may require using a SPI late data > > > sample option if the RSPI hardware has that option) > > > > > > Correct series termination of RSPI outputs (130 Ohm total for > > > 0.050" flat cable) depends on the output impedance of the RSPI > > > outputs so there's no guarantee that the added 87 ohms is correct > > > (this may also depend on RSPI output drive strength settings if > > > such things exist on the RSPI) > > > > Well, in theory, that is true. I suspect that there is a > > phase-reversal problem at these high frequencies. The probe of the > > scope adds just enough capacity to delay the signal by a fraction. > > > > At 50MHz clock, you have a phase margin of <10ns. This time is > > consumed by: - the wire-connection (~2ns per meter for copper), > > - the round-trip in the slave tranceiver (the 7i90 SPI interface), > > - the RPI buffers and SPI tranceiver. > > > > Lets assume that the wire, including PCB traces etc., takes 1ns > > (roundtrip for 25 cm). The RPI buffers and shift register are > > probably around 2ns and a bit more if it contains a glitch-filter. > > The 7i90 interface has both input buffer, an output buffer and at > > least one flip-flip propagation delay. My guess is that it would be > > about 0.5ns + 0.5ns + 2ns. > > > > That brings the grand total to 6ns, which is at 60% of the phase > > margin. This is an optimistic estimation where I specifically > > disregarded setup- and hold-times, which make things much worse. > > Assuming setup- and hold-margins on both ends (round-trip) of 0.5ns > > means adding another 2ns, resulting in 8ns total time and 80% of the > > phase margin. This is getting close to the failure point. > > > > Adding just a bit of capacity at the wrong place will make the > > signal (seemingly) slower because the flanks are less steep (as seen > > on the scope). This is enough to cause the system to fail. > > > > This also means that you cannot add external line-buffers on the > > lines. These would simply add to much delay at these frequencies > > (something like 6...10ns). Unfortunately, SPI is a synchronous and > > timing-bound propocol and cannot tolerate phase reversal. > > Is this driver your work, Bertho? > > My point is adding that 7 pf+whatever the tip clipon is, 3 or so more, > to the pi src side of the termination resistor of 82 ohms, of this > clock signal, makes it work, everytime. I think I will solder a > tightly twisted pair there for a loading cap, but that seems like such > a kludge that I'd really like to be able to test and adjust for > maximum data integrity. At some point I'll kill it again, but I might > be able to arrive at a "this size of cap is best" by using half of > what it takes to kill it again. > > Cheers, Gene Heskett
Just for S&G, I unplugged the probe from the clipon tip, leaving it hanging on the pi side of the 82 ohm resistor. Killed it completely. Read 00000000 00000000 00000000 00000000. Is it beer thirty yet? No, too hot out for alcohol. Middle 80's here. And I've not found a trimmer cap yet. 3" of tightly twisted 30 gauge I guess. If I can find a round tuit. Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) Genes Web page <http://geneslinuxbox.net:6309/gene> ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
