On Saturday 27 May 2017 15:14:55 Charles Steinkuehler wrote: > On 5/27/2017 12:21 PM, Gene Heskett wrote: > > On Saturday 27 May 2017 11:26:18 Peter C. Wallace wrote: > >> You might try lowering the series termination resistor value since > >> this looks like a possible SI issue (and the clock signal will be > >> very sensitive to SI issues). > > > > SI? Acronym for what? > > Signal integrity. > > Source, cable, and load impedance all need to match pretty well, but > you knew that already. :) > > If you're running any distance, I'd recommend a buffer on the SPI > lines. The SoC parts are designed to drive short PCB traces and > typically only have a few mA of drive, not really enough to properly > drive a cable and it's capacitance. For series termination to work > well, the driver needs enough current output to drive the full signal > across the series termination resistor. Otherwise, you wind up > needing two full cable round-trip times to get a reliable signal at > the far end, and you leave the load sitting halfway through the > transition for a cable round-trip time. > > I'd wager if you just stick a reasonably fast driver (AHCT, LVC, or > just about any 3.3V logic family) on the clock like at the RPi end to > drive the cable (with a suitable[1] series resistor, probably 25-33 > ohm), your problems will go away. > > [1] The driver output impedance plus the series termination resistor > should equal the characteristic impedance of the cable. Most cables > (ribbon with alternating ground, twisted pair Ethernet) are going to > be around 100-120 ohms. The driver needs to be able to drive a full > step (3.3V or 5V, depending on your logic family) into the effective > impedance of the cable impedance plus the driver & series terminator > (so 200-240 ohms). The I/O drivers on most SoC parts just aren't big > enough to be able to do that effectively, so it takes two round-trip > flight times to bring the load end to the final voltage, which also > typically leaves the load end sitting in the transition region for one > round-trip flight time. A recipe for problems when you're talking > about a clock line.
This all sounds like a redesign of the adapter board, with good rail bypassing at those frequencies. If thats the case, can I request that the 26 pin socket be put on the same side of the board as the 40 pinner? That would make it hang over the edge of the pi, and that would allow a 3/4" cable to be made. At what point in shortening the cable can the terms be thrown away? My mental calcs tell me the cable ringing at 1.25" would be at quite a few gigahertz, and any ringing would be faster than the semi's on either end of it can either generate or respond to, so the losses in the term resistors can be eliminated by shorting them out. In the interests of shortening this cable, the pi for this second build has been turned upside down with the 40 pin gpio placed immediately inline with the 7i90 26 pin socket with perhaps 3/4" inch between them. I could post a pix if anybody is interested. Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) Genes Web page <http://geneslinuxbox.net:6309/gene> ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
