On Thursday 19 March 2020 19:03:27 Peter C. Wallace wrote: > On Thu, 19 Mar 2020, Gene Heskett wrote: > > Date: Thu, 19 Mar 2020 18:41:42 -0400 > > From: Gene Heskett <[email protected]> > > Reply-To: "Enhanced Machine Controller (EMC)" > > <[email protected]> > > To: [email protected] > > Subject: Re: [Emc-users] A hal question? > > > > On Thursday 19 March 2020 17:27:55 Peter C. Wallace wrote: > >> On Thu, 19 Mar 2020, Gene Heskett wrote: > >>> Date: Thu, 19 Mar 2020 17:02:59 -0400 > >>> From: Gene Heskett <[email protected]> > >>> Reply-To: "Enhanced Machine Controller (EMC)" > >>> <[email protected]> > >>> To: [email protected] > >>> Subject: [Emc-users] A hal question? > >>> > >>> Greetings; I am trying to reduce the f/r error in an ATS667 based > >>> encoder. > >>> > >>> The index pulse is turned upside down by a reversal of spindel > >>> direction. Tts the nature of the beast to remain in this stable > >>> state until the approach of the triggering ferrous metal causes > >>> the first reversal which the edge ignores, and then goes back true > >>> or false as the ferrous piece crosses the center. > >>> > >>> So I break into the index signal path with a comp looking at the > >>> velocity to generate an nearly instant direction signal and use it > >>> to diddle an xor which will restore the upside down index signal > >>> to same side up, this is then fed to an edge detector which fires > >>> on the positive going edge, giving a consistent to the degree > >>> reset back to the encoder regardless of spindle direction. > >>> > >>> Does anyone see any problems with that? The reversal of the pulse > >>> at the spindle reverse point should become the out of time and > >>> possible way early pulse that sets it up to actually trigger as > >>> the piece crosses the center of the ATS667. According to my > >>> thinking anyway. > >>> > >>> Poke it full of holes if I'm wrong. > >> > >> No index patching is needed as the index is only looked at when > >> going in one direction > > > > which I would naturally define as a + output at velocity-out? > > > > The text reads like it resets the counter to zero everytime this > > index pulse goes true, although that isn't stated, could be false. > > Confusing to be sure, so which edge is the active edge when waiting > > to start a G76 or G33.1? rising or falling? the first edge as the > > index piece is approaching could have have some timing error, while > > the 2nd edge as the pole piece crosses the centerline of the hall > > elements should be pretty accurate. > > At the FPGA pin the default index polarity is falling edge (but you > can change this with the index_invert pin) > Doesn't exist. Or is this one of the fixes in the latest 7i90.zip?
Thank you Peter. Stay safe now. Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) If we desire respect for the law, we must first make the law respectable. - Louis D. Brandeis Genes Web page <http://geneslinuxbox.net:6309/gene> _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
