Signed-off-by: Stefan Tauner <[email protected]>
---
ichspi.c | 42 +++++++++++++++++++++---------------------
1 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/ichspi.c b/ichspi.c
index ed92893..0b9db20 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -43,8 +43,6 @@
#include "spi.h"
/* ICH9 controller register definition */
-#define ICH9_REG_FADDR 0x08 /* 32 Bits */
-#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
#define ICH9_REG_SSFS 0x90 /* 08 Bits */
#define SSFS_SCIP 0x00000001
@@ -66,18 +64,20 @@
#define SSFC_SCF_33MHZ 0x01000000
#define SSFC_RESERVED_MASK 0xf8008100
-#define ICH9_REG_PREOP 0x94 /* 16 Bits */
-#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
-#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
+#define ICH9_REG_FADDR 0x08 /* 32 Bits */
+#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
+#define ICH9_REG_PREOP 0x94 /* 16 Bits */
+#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
+#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
// ICH9R SPI commands
-#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
-#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
-#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
-#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
+#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
+#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
+#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
+#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
// ICH7 registers
-#define ICH7_REG_SPIS 0x00 /* 16 Bits */
+#define ICH7_REG_SPIS 0x00 /* 16 Bits */
#define SPIS_SCIP 0x0001
#define SPIS_GRANT 0x0002
#define SPIS_CDS 0x0004
@@ -94,17 +94,17 @@
bit 7 is used with fast read and one shot controls CS de-assert?
*/
-#define ICH7_REG_SPIC 0x02 /* 16 Bits */
-#define SPIC_SCGO 0x0002
-#define SPIC_ACS 0x0004
-#define SPIC_SPOP 0x0008
-#define SPIC_DS 0x4000
-
-#define ICH7_REG_SPIA 0x04 /* 32 Bits */
-#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
-#define ICH7_REG_PREOP 0x54 /* 16 Bits */
-#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
-#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
+#define ICH7_REG_SPIC 0x02 /* 16 Bits */
+#define SPIC_SCGO 0x0002
+#define SPIC_ACS 0x0004
+#define SPIC_SPOP 0x0008
+#define SPIC_DS 0x4000
+
+#define ICH7_REG_SPIA 0x04 /* 32 Bits */
+#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
+#define ICH7_REG_PREOP 0x54 /* 16 Bits */
+#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
+#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
/* ICH SPI configuration lock-down. May be set during chipset enabling. */
static int ichspi_lock = 0;
--
1.7.1
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