A good way to help speed up DRC of boards with polygon fills are:
1. If you are making the fill without spaced tracks, select only horizontal, or
vertical tracks instead of both.
2. I like to use a track & gap size 150% to 200% the size of my track-track clearance
value. This occasionally can leave a via untouched in a very congested area, but it's
rare. It can also leave small patches of area where the polygon will not reach, if
you really want these areas filled, sometimes it not much more than moving a via a few
mils.
Again, these steps are to help increase DRC speeds with polygon planes, they might
not fulfill your design needs.
_____________
Brian Guralnick
----- Original Message -----
From: "Brian Guralnick" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, June 07, 2001 8:40 PM
Subject: Re: [PEDA] DRC run times
| I find that the biggest time killer are polygon planes. For this reason, I only
|fill the polygons after everything else is done. Especially with a slow CPU.
|
| If you have polygon fills, try temporarily deleting them and run the DRC again.
|
| _____________
| Brian Guralnick
|
|
|
| ----- Original Message -----
| From: "Phil So" <[EMAIL PROTECTED]>
| To: <[EMAIL PROTECTED]>
| Sent: Thursday, June 07, 2001 7:31 PM
| Subject: [PEDA] DRC run times
|
|
| | Hello
| |
| | Does anyone know what factors affect how long the DRC in the PCB Editor
| | takes to run?
| |
| | I have a design where I have reviewed the clearance rules and netclasses. A
| | copy of the ddb file of the Rev. A design was made and renamed to be the
| | Rev. B design. The new rules were created in EXCEL, massaged with a text
| | editor and imported into the Rev. B design.
| |
| | It took 22 min, 16 sec. for the DRC to finish on the Rev. A design. It took
| | 10 sec. for the DRC to finish on the Rev. B design.
| |
| | The Rev. A design has 19 netclasses and 40 clearance rules. The Rev. B
| | design has 13 netclasses and 36 clearance rules. The new clearance rules
| | cover more "interactions" between the various nets. The new clearance rules
| | also do not have any overlap where the clearance between two nets is defined
| | by up to 4 different rules. The rules set the clearances to 0.25mm, 1.5mm,
| | 2.3mm, 3.0mm, 4.5mm and 5.5mm. Yes, lots of high voltages on this board.
| |
| | The design has 37 nets, 76 components and 212 pads and vias on it. All the
| | components are passive's. The only differences between the layout of the
| | Rev. B design and that of the Rev. A design is that about 6 tracks were
| | moved slightly or narrowed slightly to get rid of some DRC violations due to
| | the new clearance rules.
| |
| | I am using PROTEL 99SE SP3 on a 233 MHz PII with 64 MB or RAM, and NT SP4.
| |
| | Thanks in advance.
| |
| | Regards,
| |
| | Philip So
| | Electronics Design Engineer
| | PDL Electronics Ltd
| | 81 Austin Street
| | Napier
| | New Zealand
| |
| | Phone :++64 6 843 5855 ext. 7152
| | Fax :++64 6 843 0603
| | E-mail :[EMAIL PROTECTED]
| |
| | Visit our website: http://www.pdl.co.nz
| |
| |
| | The contents of this E-mail may contain information that is legally
| | privileged and/or confidential to the named recipient. This information is
| | not to be used by any other person and/or organisation. The views expressed
| | in this document do not necessarily reflect those of the company.
| |
| |
| |
|
|
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