At 10:45 AM 6/12/01 -0700, Brad Velander wrote:
> At it's default settings the ERC matrix only gives a warning for a
>couple of possible open wire scenarios, I assume that your case was not one
>that generated a warning.
As Brad mentioned or implied, the ERC matrix can be set for more thorough
checking of connections. Most of us recommend that all unconnected pins, of
any kind, be flagged with a warning at least, if they have not been
suppressed with No-ERC Directives. Then one can verify that all of these
warnings represent intentionally open pins, and more No-ERC Directives placed.
If one has any doubt about connectivity -- there can be some obscure
situations -- a No-ERC Directive should not be placed until it has been
verified that the net list is correct. Even then it would be better to find
out why the mysterious warning or error is being created.
But there are some conditions which cannot, by their nature, be detected,
at least not with anything like the current state of the art. Consider a
net with a single driving output, two inputs, and one passive pull-up.
If the net is broken by a bad net name into two sections:
(1) output, input 1
(2) input 2, passive
With the normal ERC matrix, both nets meet the criteria to be acceptable.
One might check the passive/input combination as meriting a warning, and
then suppress the warnings that come, either while drawing the schematic or
with the first ERC passes, but I don't know anyone who is doing that, even
though it might not be a bad idea.
To avoid split nets from misnaming:
(1) Use Sheet Symbol / Port Connection scope, *and*
(2) Generate a list of nets for each sheet and look it over for possible
"duplications." If you find two nets, DATA1 and DATAl, which *are*
different from each other, you've got a problem.
(If you allow Net Labels to be global, it becomes much more difficult to
check; SS/PC connectivity makes Net Labels important only at the sheet
level, so you can check it sheet by sheet. A similar argument applies to
Only Ports Global, except that there is less potential for error because
the net labels, at least, are eliminated as a problem.)
(A more sophisticated checker might look for certain kinds of net name
similarities and flag them with a suppressable warning. Frankly, such
similarities deserve the label of *error*, for they will seriously confuse
a poor technician who encounters them.)
Since this seems to have been overlooked by one reader, I'll repeat: using
any scope other than SS/PC when design pages are being recycled from other
schematics is begging for trouble.
Yes, there are plenty of designers using Net Labels and Ports Global, or
Only Ports Global, but wait until they get older and find they can keep
less information in their heads; they'll come around. Using NL/PC or OPG
may save a little time, because there is no need to wire a top level; but
like many practices that save a little time, it can bite you when you least
expect it.
A bonus: a well-drawn SS/PC schematic, with its explicit top-level
connections, and if the sheet divisions are rational, will normally be much
easier to understand than the other forms of multipage schematics.
I think that connectivity scope should be a schematic attribute; I'm not
sure that it is; I suspect that the scope defaults to the last-used scope.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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