Re: [PEDA] Quickly checking sync status between PCB & schematic

[van de Werken, Matthew (DEM, PH)]

Thanks Abd ul-Rahman, I think I'll go with (2). There are some other
"issues" with the whole ddb at the moment, so at least I can put it off for
a little bit longer...

Unfortunately, I *am* the "cheapest" solution, since (by accident) this is
part of my job description (mostly because no-one else will touch it and I
can't stand to have the system out of whack).

I guess now is a good time to start to learn Client Basic...

Cheers,
Matthew van de Werken
Electronics Engineer
CSIRO Exploration & Mining - Gravity Group
1 Technology Court - Pullenvale - Qld - 4069 - AUSTRALIA
ph:  +61-7-3327 4685     fax:  +61-7-3327 4455
email:  [EMAIL PROTECTED]


> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 28 June 2001 12:29
> To: Protel EDA Forum
> Subject: Re: [PEDA] Quickly checking sync status between PCB 
> & schematic
> 
> 
> At 09:45 AM 6/28/01 +1000, van de Werken, Matthew (DEM, PH) wrote:
> 
> >Is there a quick way of checking the state, without actually 
> doing the
> >synchronisation? I have around a hundred or so boards to 
> check in 3 ddb's,
> >so I'd really like this to be quick. I HATE doing the same 
> thing over and
> >over (and I also HATE fixing other people's mess, but anyway...).
> 
> There a number of ways to do this, I don't know which is the fastest.
> 
> (1) You could use the synchronizer. You want to preview the 
> changes, not 
> make them. Uncheck just about everything, you want to 
> "synchronise" only 
> the net assignments. You can then generate a report. Don't let the 
> synchronizer complete until you know what is going on, good 
> chance the 
> board is correct and the schematic is not, particularly if 
> the designers 
> have been sloppy.
> 
> (2) Generate a net list from the PCB and a netlist from the 
> schematic and 
> use the netlist comparison tool in Schematic (I think it is 
> Reports/Compare 
> Netlists). The netlists should be identical. It would also be 
> a good idea 
> to run DRC in the PCB as well as ERC in the schematic. Again, if the 
> designers were sloppy, expect the latter to be a big mess. But clean 
> documentation, properly configured will DRC and ERC with no 
> errors, almost 
> without exception.
> 
> (3) Create a netlist from the Schematic and load this into 
> the PCB. If 
> there are any duplicate pad names (such as multiple instances of 
> J1-SHIELD), this could be problematic, but most designs don't 
> have these.
> 
> My a priori preference would be for (2), precisely because it 
> is the same 
> thing, over and over. Sorry....
> 
> You might be able to make some macros that would speed it up. Or hire 
> someone else to do it. I've got contacts for inexpensive 
> design support, so 
> contact me directly if you are interested in this.
> 
> 
> 
> Abd ul-Rahman Lomax
> LOMAX DESIGN ASSOCIATES
> PCB design, consulting, and training
> Protel EDA license resales
> Sonoma, California, USA
> (707) 939-7021, efax (419) 730-4777
> [EMAIL PROTECTED]
> [EMAIL PROTECTED]
> 
> 

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