Hi Jeroen , David
I'm interested in assisting where I can in the whole freeDV sphere. I've
recently gone over the last year of forum posts to see what I have
missed in detail.
I'd like to be able to implement LPC122, 203 (and Codec2) on a small ,
cheap FPGA for use with FreeDV .
I am not sure if this discussion needs a separate forum. Please let me know.
I'm going to take a look at the code and understand how suited to a
processor or an FPGA from a cost/power point of view. I am a XIlinx user
, and I am also a XIlinx Alliance Partner, so I get access to cool stuff.
As you know, complex algorithms are generally best executed (and more
quickly programmed and debugged) on a processor, until you run out of
speed or power, at which the programmer gradually hands over more and
more of the work to an FPGA co processor.
3 to 6 GFLOPS is of course no space for an STM32. But might be good as
a FPGA co processor for an STM32, to execute both CODEC2 and LPCNET and
take the heavy lifting out of the STM32 and turn the codec job into a
SPI peripheral.
I am thinking a medium Spartan7 (maybe $10-$20) or a small ZYNQ (single
core Cortex A9 and a heap of FPGA fabric $20-$30)
Smartphone cores are good, but running flat out for more than a few
seconds they (can) burn up . Sure they decode video, but that's on
dedicated hard blocks.
let me know what you think.
Another thing- Jeroen, if you would like me to organise a XIlinx U50
card to the task, I think my personal finances could stretch that. (or
I could head down that road to make things fast to develop)
https://www.xilinx.com/publications/product-briefs/alveo-u50-product-brief-v2.pdf
https://www.xilinx.com/support/documentation/data_sheets/ds965-u50.pdf
https://www.xilinx.com/products/boards-and-kits/alveo/u50.html
Xilinx have wrapped an easy to use framework around it. That's not the
sort of FPGA I am proposing, but it is a useful method of running up
testing with great speed. The FPGA has 8 GBytes of essentially 1024 bit
wide full core speed memory....a 10k$ FPGA.
73
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