Hi Steve
oh yeah. Undergrad thesis. good for students to have a real project.
--and the thesis is a useful metric
Verilog. yuk.
The other option is HLS. C++ >> VHDL. You need to somewhat know what you
are doing, because what you do affects how much of a mess it makes at
the low level.... but it is capable of spectacular results .
On 22/06/2020 1:47 pm, Steve wrote:
FYI
Codec2 (2400 I think) Encoder in FPGA
Thesis:
https://etd.ohiolink.edu/!etd.send_file?accession=miami158819886466373&disposition=inline
Github: https://github.com/santhiyaskumar/FPGA_Codec2Encoder
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