Hi Steve
Yeah
I am really impressed with it (as much as codec2).
alright I'll start digging through it and understanding LPCnet
computational requirements.
the idea being we'd end up with a codec2 and LPCnet co-processor on a
SPI interface etc.
or we end up with an SM2000- using a ZYNQ, *might* get away without any
external DRAM,. (which might make life easier ). - just use on chip RAM
memory (256kBytes) and lock the largeish L2 cache.
If the NEON core on the 666 MHz CortexA9 (ZYNQ+FPGA) is useful, then it
makes sense to use it, otherwise, just std Spartan7 and microblaze for
rough stuff. The Cortex A9 is useful because being an out of order
processor, its quite good at making the most of any code, data hazards
aside. The Zynq has a 12 bit ADC, and MUX also. useful.
g
On 22/06/2020 2:18 pm, Steve wrote:
Hee,
There's also nMigen
https://www.youtube.com/watch?v=85ZCTuekjGA
Although the guy never finishes anything :-) The ride was interesting.
On Sun, Jun 21, 2020 at 11:15 PM glen english <[email protected]
<mailto:[email protected]>> wrote:
Hi Steve
oh yeah. Undergrad thesis. good for students to have a real project.
--and the thesis is a useful metric
Verilog. yuk.
The other option is HLS. C++ >> VHDL. You need to somewhat know
what you
are doing, because what you do affects how much of a mess it makes at
the low level.... but it is capable of spectacular results .
On 22/06/2020 1:47 pm, Steve wrote:
> FYI
>
> Codec2 (2400 I think) Encoder in FPGA
>
> Thesis:
>
https://etd.ohiolink.edu/!etd.send_file?accession=miami158819886466373&disposition=inline
>
>
> Github: https://github.com/santhiyaskumar/FPGA_Codec2Encoder
>
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Glen English
RF Communications and Electronics Engineer
CORTEX RF
&
Pacific Media Technologies Pty Ltd
ABN 40 075 532 008
PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077
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