As for the G5, moving 64 bit addresses around takes longer and uses more power than moving a 32 bit address.
The memory bus is parallel, not serial. All 64 address lines latch simultaneously, ditto for the data responses.
Yes, but if a CPU is running in a 64 bit address space, it has to use 8 byte pointers while a 32 bit address space only requires a 4 byte pointer. In a single fetch or store to a 64 bit wide memory bus the 64 bit program can process one pointer while the 32 bit program can process two. If you don't need the larger address space and/or 64 bit math then 64 bit operation extracts a penalty.
There are lot of problems with using the G5 CPU and chipset in a laptop, which I discuss further down.
As to raw bus speed, one of the big advantages of the G5 is that Apple has boosted the bus to a full 1 GHz.
Yes, but a G4 could also be built with a 1 GHz bus. Motorola, get your head out of the sand.
For a 1 GHz processor, this means a multiplier of 1:1 -- the ideal configuration. And for a 2 GHz system, 2:1 is still great. Heck, even 3:1 will still rock. Memory busses don't really become a bad problem until 6:1 or so.
Capability-wise, the G5 can blow the doors off a G4. It's just a matter of the software catching up to it.
But it's not because the G5 is a 64 bit CPU. The bus bandwidth is a major contributor as well as a more optimized CPU engine.
When a program is recompiled to run in a 64 bit memory space it will get slower, unless perhaps it uses a lot of 64 bit integer math operations which conceivably could execute faster. But 64 bit integer operations are not that useful in the real world, and I have a hard time imagining a program where the 64 bit integer math speedup would compensate for the cost of 64 bit pointers
The real issue right now is heat and power.
Agreed. And also the chips are very big and expensive with lots of pins.
Apple went with Motorola's new G4-class processor this round because it uses less power than the previous rev. But IBM is catching up. Their currently-sampling 90nm (I think that's the right size) chips are showing great promise. They even have a variable clock rate - great for lower-power modes.
My point is that there is a lot of room to improve performance in a 32 bit updated G4 design yet keep the power down. I think, given the power and heat limitations of a laptop that a highly optimized 32 bit CPU would hit the sweet spot.
The G5 does not have a memory bus on it, rather is has dual, one for read and one for write, 32 bit busses that connect to the northbridge chip. The northbridge has two sets of these busses to support dual CPU's. There are costs in silicon, package size, and power dissipation to this approach. The G5 northbridge is a very big chip. Apple's design uses a heat pipe just to cool the northbridge. There are four heatpipes for each G5 CPU and one heat pipe for each CPU low voltage power supply MOSFETs. That is 11 heat pipes total in an Apple dual G5.
A more optimal approach for single CPU operation would be to put the DDR SDRAM memory interface on the CPU with a secondary high speed bus (HyperTransport ?) for the I/O interface. This gives the CPU the fastest possible path to DDR SDRAM, cuts pin counts drastically, and reduces power dissipation.
I'll go out on a limb and say that the current G5 CPU/northbridge design will NEVER make it into a production laptop computer.
Paul
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