From: Nancy Haitz <[EMAIL PROTECTED]>
Date: Wed, 10 Aug 2005 15:59:06 -0400
Joy wrote:
How do you know this? What factors are you looking at to determine
that? CAS
or CL rating? Speed (3-2-2, 2-2-2, etc. or PC66 vs 100 vs 133)?
Density?
(what is a low density DIMM anyway?)
I am far from a RAM expert. Maybe Jeff will notice this post and offer
up some details.
When things switched to SDRAM I did not keep up very well. The
PC66/100/133 are just speed ratings, analogous to the 50, 60, 70, 80
etc ns ratings on FPM RAM. It's a little different because SDRAM is
Synchronous-DRAM which means it runs to the beat of a clock signal.
So the 66, 100 or 133 are the speeds of clocks with which that kind
of SDRAM can run.
I am not current with CAS and CL but I wrote half of an SDRAM
controller once. :-) I suspect that those items have to do with how
many clock beats it takes the SDRAM to respond to certain commands or
conditions.
Date: Wed, 10 Aug 2005 15:03:00 -0500
Subject: Re: [G] DIMM saga continues
From: Joy Freeman <[EMAIL PROTECTED]>
"IF this OWC100SD256324 256MB Module is not compatible with your Blue &
White G3 Powermac, the only 256MB module we know of that will work is a 16x8
based 256MB, such as OWC100SD256168 which, unfortunately, is nearly double
the cost."
Okay, so maybe this is my problem, and my (more expensive, of course!)
solution. But I am still curious. Can anyone tell me exactly what 16x8 (and
32x4) means?
16 X 8 means 16 million addresses by 8 bits wide and is more properly
written 16M X 8. 32 X 4 is 32 million addresses by 4 bits wide. The
former has 16 million storage locations that can hold 8 bits each.
The latter has 32 million storage locations that can hold 4 bits
each. However, both of these chips has a total capacity of 128
million storage locations (bits). In other words each chip has the
same total capacity, but it is organized differently.
DIMMs are 64 bits wide. That means that your computer reads (or
writes) 64 bits (8 bytes) from a DIMM per operation. No memory chip
made is 64 bits wide. So they put several memory chips on a DIMM and
run them in parallel to supply the 64 bits. Every chip receives the
same address information and the same command information and then
they all supply the requested data together.
So, if you have eight 16M X 8 bit memory chips running in parallel,
they form a 64 bit wide memory storage device with 16 million
addresses. 16 million X 8 bytes wide (64 bits wide = 8 bytes wide) =
128 MB of total capacity.
To further complicate matters, there may be two (or more) banks on a
single DIMM. In this case the DIMM is sort of treated as if it is
two separate DIMMs. So you could put sixteen chips each of 16M X 8
capacity on a DIMM, divide it into two banks, and you'd have 128 +
128 = 256 MB of capacity.
A 32M X 4 chip would have 32 million addresses but each address only
stores 4 bits. So it takes sixteen 32M X 4 chips to create a 64 bit
wide DIMM. So sixteen 32M X 4 chips forms a DIMM of 32 million X 64
bits or 32M X 8 bytes = 256 MB.
Notice that in the second case all 256 MB is in one bank. So to
address anything in the second DIMM, one must send the address
signals to sixteen chips at a time. However, in the first DIMM, one
must only send signals to eight chips at a time. Of course, one
changes which eight chips depending on what wishes to address.
Each chip receiving a signal uses some current or signal strength.
So the total signal strength needed to address the sixteen 32 X 4
built DIMM is twice as large as the signal strength needed to address
the eight 16 X 8 built DIMM. This is likely the source of the
incompatibility.
The memory controller in the problem machines probably only has
enough strength to signal 8 chips at a time. At any rate, it does
not have the strength to signal sixteen at a time.
So even if DIMMs are built with chips that have identical capacities,
a difference in organization can make a big difference in how they
work.
Now if the above was a bit confusing, consider the old 30 pin SIMMs
which were a mere 8 bits wide. They had eight chips on them. Each
chip supplied just one bit. So those were very simple. On a 1 MB
SIMM you might find eight 1M X 1 chips. You put eight chips together
to get a 1 byte wide SIMM and the capacity of the SIMM was the number
of addresses of the chips. A 16 MB SIMM would have eight 16M X 1
chips on board.
Jeff Walther
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