[Bug target/108177] MVE predicated stores to same address get optimized away

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108177

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
I suspect

(insn 10 9 11 2 (set (mem:V16QI (reg/v/f:SI 117 [ pa ]) [0 MEM[(signed char[16]
*)pa_2(D)]+0 S16 A8]) 
        (unspec:V16QI [
                (reg/v:V16QI 116 [ a ])
                (reg:V16BI 120)
            ] VSTRBQ_U)) "include/arm_mve.h":12501:3 4673 {mve_vstrbq_p_uv16qi}
     (nil)) 

isn't a very accurate description of a masked store.  On x86 we have

(insn 17 16 0 (set (mem:V8DI (reg/v/f:DI 87 [ p ]) [0  S64 A8])
        (vec_merge:V8DI (reg:V8DI 92)
            (mem:V8DI (reg/v/f:DI 87 [ p ]) [0  S64 A8])
            (subreg:QI (reg:SI 95) 0)))
"/home/rguenther/obj-trunk-g/gcc/include/avx512fintrin.h":6484:3 -1

For AVX we use:

(define_expand "maskstore<mode><sseintvecmodelower>"
  [(set (match_operand:V48_AVX2 0 "memory_operand")
    (unspec:V48_AVX2
      [(match_operand:<sseintvecmode> 2 "register_operand")
       (match_operand:V48_AVX2 1 "register_operand")
       (match_dup 0)]
      UNSPEC_MASKMOV))]
  "TARGET_AVX")

note how the memory destination is also an input to the UNSPEC here.