[Bug target/99195] Optimise away vec_concat of 64-bit AdvancedSIMD operations with zeroes in aarch64

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99195

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>:

https://gcc.gnu.org/g:d1e7f9993084b87e6676a5ccef3c8b7f807a6013

commit r14-651-gd1e7f9993084b87e6676a5ccef3c8b7f807a6013
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Wed May 10 10:40:06 2023 +0100

    aarch64: PR target/99195 annotate simple narrowing patterns for
vec-concat-zero

    This patch cleans up some almost-duplicate patterns for the XTN, SQXTN,
UQXTN instructions.
    Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and
!BYTES_BIG_ENDIAN cases,
    as well as the intrinsic expanders that select between the two.
    Tests are also added. Thankfully the diffstat comes out negative \O/.

    Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

    gcc/ChangeLog:

            PR target/99195
            * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le):
Delete.
            (aarch64_xtn<mode>_insn_be): Likewise.
            (trunc<mode><Vnarrowq>2): Rename to...
            (trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
            (aarch64_xtn<mode>): Move under the above.  Just emit the truncate
RTL.
            (aarch64_<su>qmovn<mode>): Likewise.
            (aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
            (aarch64_<su>qmovn<mode>_insn_le): Delete.
            (aarch64_<su>qmovn<mode>_insn_be): Likewise.

    gcc/testsuite/ChangeLog:

            PR target/99195
            * gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.