This patch updates the instruction length for 128-bit move insns for types that
go into a single vector register. It is a lot simpler than the previous patch,
which was written before I added the prefixed_length and non_prefixed_length
attributes.
Along with the other patches, I have done bootstraps on a little endian power8
system, and there were no regressions in the test suite. Can I check this into
the trunk?
2019-10-08 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Make sure the
instruction length is correct for prefixed loads and stores.
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 276713)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -1149,10 +1149,14 @@ (define_insn "vsx_mov<mode>_64bit"
"vecstore, vecload, vecsimple, mffgpr, mftgpr, load,
store, load, store, *, vecsimple,
vecsimple,
vecsimple, *, *, vecstore, vecload")
- (set_attr "length"
+ (set_attr "non_prefixed_length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
+ (set_attr "prefixed_length"
+ "*, *, *, 8, *, 20,
+ 20, 20, 20, 8, *, *,
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
