Re: [PATCH] V5, #6 of 15: Make vector load/store instruction length correct with prefixed addresses

[Michael Meissner]

On Fri, Oct 11, 2019 at 04:53:23PM -0500, Segher Boessenkool wrote:
> Hi!
> 
> On Wed, Oct 09, 2019 at 04:26:20PM -0400, Michael Meissner wrote:
> > --- gcc/config/rs6000/vsx.md        (revision 276713)
> > +++ gcc/config/rs6000/vsx.md        (working copy)
> > @@ -1149,10 +1149,14 @@ (define_insn "vsx_mov<mode>_64bit"
> >                 "vecstore,  vecload,   vecsimple, mffgpr,    mftgpr,    
> > load,
> >                  store,     load,      store,     *,         vecsimple, 
> > vecsimple,
> >                  vecsimple, *,         *,         vecstore,  vecload")
> > -   (set_attr "length"
> > +   (set_attr "non_prefixed_length"
> >                 "*,         *,         *,         8,         *,         8,
> >                  8,         8,         8,         8,         *,         *,
> >                  *,         20,        8,         *,         *")
> > +   (set_attr "prefixed_length"
> > +               "*,         *,         *,         8,         *,         20,
> > +                20,        20,        20,        8,         *,         *,
> > +                *,         20,        8,         *,         *")
> 
> Alternative 13 has non_prefixed_length 20, I wonder what insns that
> generates?

All of the vector constants that match the constants matched by
easy_altivec_constant.

For example:

        vector int foo (void)
        {
          return (vector int) { 0, 0, 0, 1 };
        }

generates:

        vspltisw 2,0
        vspltisw 0,1
        vsldoi 2,0,2,12

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797