Christophe Lyon <christophe.l...@linaro.org> writes:
[...]
>> I think you need to add -mfloat-abi=hard to the dg-additional-options
>> otherwise vld1_lane_bf16_1.c
>> fails on targets with a soft float-abi default (eg arm-linux-gnueabi).
>>
>> See bf16_vldn_1.c.
>
> Actually that's not sufficient because in turn we get:
> /sysroot-arm-none-linux-gnueabi/usr/include/gnu/stubs.h:10:11: fatal
> error: gnu/stubs-hard.h: No such file or directory
>
> So you should check that -mfloat-abi=hard is supported.
>
> Ditto for the vst tests.
Hi Christophe,
this patch should implement your suggestions.
On my arm-none-linux-gnueabi setup the tests were already skipped
as unsupported so if you could test and confirm this fixes the
issue you see would be great.
Thanks!
Andrea
>From d27e3f39fa2f348a4b8aa929bbb65808a09f1211 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.cora...@arm.com>
Date: Thu, 5 Nov 2020 08:57:03 +0000
Subject: [PATCH] arm: [testcase] Better narrow some bfloat16 testcase
2020-11-05 Andrea Corallo <andrea.cora...@arm.com>
* gcc.target/arm/simd/vld1_lane_bf16_1.c: Add -mfloat-abi=hard
flag.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_1.c: Likewise.
* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_v8_2a_bf16_neon_ok_nocache): Require
target to support -mfloat-abi=hard.
---
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c | 2 +-
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c | 1 +
gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c | 1 +
gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c | 2 +-
gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c | 1 +
gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c | 1 +
gcc/testsuite/lib/target-supports.exp | 4 ++++
7 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
index fa4e45b7217..64e1f394676 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c
@@ -1,7 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
index c83eb53234d..9e56c25974e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
index 8e21e61c9c0..c75d24db11b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
index e018ec6592f..77e8a3bd5eb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c
@@ -1,7 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
-/* { dg-additional-options "-O3 --save-temps" } */
+/* { dg-additional-options "-O3 --save-temps -mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
index 39870dc054c..ba4017afd0c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
index f31bd120fc2..4c96b491fb2 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c
@@ -1,6 +1,7 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
+/* { dg-additional-options "-mfloat-abi=hard" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 15f0649f8ae..2ab7e39756d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5213,6 +5213,10 @@ proc
check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
return 0;
}
+ if { ! [check_effective_target_arm_hard_ok] } {
+ return 0;
+ }
+
foreach flags {"" "-mfloat-abi=hard -mfpu=neon-fp-armv8"
"-mfloat-abi=softfp -mfpu=neon-fp-armv8" } {
if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object
{
#include <arm_neon.h>
--
2.20.1
