[PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[YunQiang Su]

If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.

gcc/ChangeLog:

        * config/mips/mips.cc (mips_expand_prologue):
          IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..d823c459b75 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
              if (!cfun->machine->keep_interrupts_masked_p
                  && cfun->machine->int_mask == INT_MASK_EIC)
                emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-                                      GEN_INT (6),
+                                      TARGET_MCU ? GEN_INT (8) : GEN_INT (6),
                                       GEN_INT (SR_IPL),
                                       gen_rtx_REG (SImode, K0_REG_NUM)));
 
-- 
2.30.2