在 2022/2/12 16:47, Maciej W. Rozycki 写道:
On Fri, 11 Feb 2022, Jeff Law wrote:
If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.
gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_prologue):
IPL is 8bit for MCU ASE.
OK
But this is still wrong AFAICT.
Yes. you are right.
The mask is applied to the CP0 Status register according to the comment,
but the layout of the interrupt bit-field is different between the CP0
Status and the CP0 Cause registers, so you can't just extract it from one
of the two registers and directly apply to the other.
Since our case has 128 interrupts, so I didn't find this problem.
I would like to know how this code has been verified.
And now new version sent with the test with 256 interrupts.
See v3 please.
Maciej
.
