On Tue, 15 Mar 2022, YunQiang Su wrote: > If MIPS MCU extension is enable, the IPL section in Cause and Status > registers has been expand to 8bit instead of 6bit. > > In Cause: the bits are 10-17. > In Status: the bits are 10-16 and 18. > > MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.
I can see you have committed this change, but I cannot see an approval posted to the mailing list. Who has approved your change? > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc > index a1c4b437cd4..91e1e964f94 100644 > --- a/gcc/config/mips/mips.cc > +++ b/gcc/config/mips/mips.cc > @@ -12254,10 +12254,22 @@ mips_expand_prologue (void) > /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ > if (!cfun->machine->keep_interrupts_masked_p > && cfun->machine->int_mask == INT_MASK_EIC) > - emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > - GEN_INT (6), > + { > + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > + TARGET_MCU ? GEN_INT (7) : GEN_INT (6), > GEN_INT (SR_IPL), > gen_rtx_REG (SImode, K0_REG_NUM))); > + if (TARGET_MCU) > + { > + emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), > + gen_rtx_REG (SImode, K0_REG_NUM), > + GEN_INT (7))); > + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > + GEN_INT (1), > + GEN_INT (SR_IPL+8), > + gen_rtx_REG (SImode, K0_REG_NUM))); > + } > + } While code generation has been corrected your change has code formatting issues which should have been addressed before committing. A test case should have been made too. Maciej