From: Christoph Müllner <christoph.muell...@vrull.eu> This series introduces support for the T-Head specific RISC-V ISA extensions which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here: https://github.com/T-head-Semi/thead-extension-spec The series begins with two preparation patches, that do not introduce any functional changes. The first patch just fixes the comment order to the code order. And the second patch restructures the register save/restore code in the CFA expansion, which simplifies the XTheadMemPair patch. This series adds basic support (i.e. awareness of the extension name and test macro) for the following XThead* extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadInt * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The series includes optimizations for most of these extensions (the exceptions are XTheadInt and XTheadMemIdx). The series also introduces support for "-mcpu=thead-c906", which also enables all available XThead* ISA extensions of the T-Head C906. All patches have been tested and don't introduce regressions for RV32 or RV64. Therefore partial inclusion of this series is possible. Christoph Müllner (10): riscv: attr: Synchronize comments with code riscv: Restructure callee-saved register save/restore code riscv: Add basic XThead* vendor extension support riscv: riscv-cores.def: Add T-Head XuanTie C906 riscv: thead: Add support for the XTheadBa ISA extension riscv: thead: Add support for the XTheadBs ISA extension riscv: thead: Add support for th XTheadBb ISA extension riscv: thead: Add support for XTheadCondMov ISA extensions riscv: thead: Add support for XTheadMac ISA extension riscv: thead: Add support for XTheadFmv ISA extension moiz.hussain (1): riscv: thead: Add support for XTheadMemPair ISA extension gcc/common/config/riscv/riscv-common.cc | 26 + gcc/config/riscv/bitmanip.md | 52 +- gcc/config/riscv/constraints.md | 8 + gcc/config/riscv/iterators.md | 4 + gcc/config/riscv/peephole.md | 298 ++++++ gcc/config/riscv/predicates.md | 4 + gcc/config/riscv/riscv-cores.def | 4 + gcc/config/riscv/riscv-opts.h | 26 + gcc/config/riscv/riscv-protos.h | 11 +- gcc/config/riscv/riscv.cc | 919 ++++++++++++++++-- gcc/config/riscv/riscv.md | 72 +- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/thead.md | 385 ++++++++ .../gcc.target/riscv/mcpu-thead-c906.c | 28 + .../gcc.target/riscv/xtheadba-addsl.c | 55 ++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + .../gcc.target/riscv/xtheadbb-extu.c | 22 + gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 + .../gcc.target/riscv/xtheadbb-srri.c | 21 + gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 + .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 + .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 + .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 + .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 + .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 + .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 + .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 + .../gcc.target/riscv/xtheadcondmov.c | 14 + .../gcc.target/riscv/xtheadfmemidx.c | 14 + .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 + gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + .../gcc.target/riscv/xtheadmempair-1.c | 29 + .../gcc.target/riscv/xtheadmempair-10.c | 36 + .../gcc.target/riscv/xtheadmempair-11.c | 18 + .../gcc.target/riscv/xtheadmempair-12.c | 20 + .../gcc.target/riscv/xtheadmempair-13.c | 23 + .../gcc.target/riscv/xtheadmempair-14.c | 30 + .../gcc.target/riscv/xtheadmempair-15.c | 15 + .../gcc.target/riscv/xtheadmempair-16.c | 18 + .../gcc.target/riscv/xtheadmempair-17.c | 13 + .../gcc.target/riscv/xtheadmempair-18.c | 49 + .../gcc.target/riscv/xtheadmempair-19.c | 86 ++ .../gcc.target/riscv/xtheadmempair-2.c | 26 + .../gcc.target/riscv/xtheadmempair-20.c | 21 + .../gcc.target/riscv/xtheadmempair-3.c | 30 + .../gcc.target/riscv/xtheadmempair-4.c | 20 + .../gcc.target/riscv/xtheadmempair-5.c | 21 + .../gcc.target/riscv/xtheadmempair-6.c | 19 + .../gcc.target/riscv/xtheadmempair-7.c | 22 + .../gcc.target/riscv/xtheadmempair-8.c | 29 + .../gcc.target/riscv/xtheadmempair-9.c | 37 + .../gcc.target/riscv/xtheadmempair-helper.h | 52 + .../gcc.target/riscv/xtheadmempair.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + 65 files changed, 3116 insertions(+), 92 deletions(-) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-helper.h create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c -- 2.38.1
