Re: [PATCH] RISC-V: Add conditional sign/zero extension and truncation autovec patterns

[Robin Dapp via Gcc-patches]

Hi Lehua,

thanks, just tiny non-functional nits.

> -  rtx ops[] = {operands[0], quarter};
> -  icode = code_for_pred_trunc (<V_QUAD_TRUNC>mode);
> -  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops);
> +  rtx half = gen_reg_rtx (<V_QUAD_TRUNC>mode);

Not really a half anymore now? :)

> +#include <stdint.h>
> +
> +#define DEF_LOOP(OLD_TYPE, NEW_TYPE)                                         
>   \
> +  void __attribute__ ((noipa))                                               
>   \
> +  test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,                    
>   \
> +                               OLD_TYPE *__restrict a,                      \
> +                               NEW_TYPE *__restrict b,                      \
> +                               OLD_TYPE *__restrict pred, int n)            \
> +  {                                                                          
>   \
> +    for (int i = 0; i < n; ++i)                                              
>   \
> +      {                                                                      
>   \
> +     NEW_TYPE bi = b[i];                                                    \

Is this necessary for recognizing a different pattern?

> +/* wider-width Integer Type => Integer Type */

Isn't it the other way around or am I just confused?

> +/* narrower-width Integer Type => Integer Type */
> +#define TEST_ALL_X2X_NARROWER(T)                                             
>   \
> +  T (uint16_t, uint8_t)                                                      
>   \

Same here.

Regards
 Robin