I have also recently become interested in a GCC port for the 18F.
Can someone summarize who--if anyone--is working on this, how much progress he has made so far (Is his work based on mainline?), and any expected future milestones?
(And who are all of the people in the CC list? Is there some other list discussing this?)
I think that the major work that will need to be done for this port is figuring out how to get segmentation to work. Some other potential ports need this too, so if there's any way to do this in a way that all ports can benefit, that would be great. I think this is definitely possible, but it seems like it may take some effort--particularly to get the changes into a form acceptable for inclusion into FSF GCC.
The way I would do this (and will, perhaps, if noone else intends to work on this any time soon) is to consider the access bank (low 128 GPRs and some of the high 128 SPRs) as the GCC registers. (I am not sure if ~140 registers is too many for GCC to handle effectively; Are there ports that use this many?) This will yield a port that can deal with at least 512 bytes of memory, I think. Implementing segmentation will give it access to the rest of the banks.
