daniel tian wrote:
> That seems to solving a address mode problem. My problem is that while
> loading a large immediate data or SYMBOL_REF, the destination is a
> specified general register (register 0:R0). So I don't how to let the
> define_expand "movsi" pattern to generate destination register in R0.
Well, the RTL that you emit in your define_expand has to match an insn
pattern in the end, so you could make an insn for it that uses a predicate and
matching constraint to enforce only accepting r0. If you use a predicate that
only accepts r0 you'll get better codegen than if you use a predicate that
accepts general regs and use an r0-only constraint to instruct reload to place
the operand in r0.
cheers,
DaveK
