2009/2/27 Dave Korn <dave.korn.cyg...@googlemail.com>:
> daniel tian wrote:
>
>> That seems to solving a address mode problem. My problem is that while
>> loading a large immediate data or SYMBOL_REF, the destination is a
>> specified general register (register 0:R0). So I don't how to let the
>> define_expand "movsi" pattern to generate destination register in R0.
>
> Well, the RTL that you emit in your define_expand has to match an insn
> pattern in the end, so you could make an insn for it that uses a predicate and
> matching constraint to enforce only accepting r0. If you use a predicate that
> only accepts r0 you'll get better codegen than if you use a predicate that
> accepts general regs and use an r0-only constraint to instruct reload to place
> the operand in r0.
Well, I have already done this. There is insn pattern that the
predicate limits the operand in R0. But if in define_expand "movsi" do
not put the register in R0, the compiler will crashed because of the
unrecognized RTL(load big immediate or Symbol). Like the below:
(define_insn "load_imm_big"
[(set (match_operand:SI 0 "zero_register_operand" "=r")
(match_operand:SI 1 "rice_imm32_operand" "i"))
(clobber (reg:SI 0))]
"TARGET_RICE"
{
return rice_output_move (operands, SImode);
}
)
PS:rice_output_move is function to output assemble code.
Thanks.
