On Thu, 28 Feb 2013, Paulo Matos wrote: > Hello, > > I am looking at how to correctly model in GCC predicate > registers that have more than one bit and the value set into to > the predicate register after a comparison depends on the size > of the comparison. > > I have looked into GCC backends but haven't really found any > backend with a similar constraint. Have I missed a backend that > has similar requirements?
Except for CCmodes being dependent on source-modes, I'd sneak peeks at PowerPC. > If not, is there any way to currently > (as of HEAD) model this in GCC? IIUC, this sounds simply like having multiple separate condition-code registers, just with a size-dependent CCmodes twist; for each type of comparison where there'd be a separate CCmode variant, you also need separate CCmodes for each source mode M, all separated in cbranchM4 and cstoreM4. brgds, H-P
