On 05/07/2015 10:59 AM, Uros Bizjak wrote: > If we consider SSE operations as DImode operations, we will loose the > ability to precisely specify which operation (SSE vs. general reg) we > want. I'm afraid that in DImode case, combine will choose FLAG-less > pattern that will mandate moves from general regs to SSE regs and > back. This was the reason to invent V1DImode/V1TImode "vectors" to > avoid moving double-mode values to MMX/SSE regs for double-mode > shifts.
It would of course have to be a combined pattern. The problem being addressed by V1TImode is that SSE doesn't really support TImode arithmetic. We've got some logical operations and restricted shifting, but no addition, multiplication, or fully general shifting. The problem being addressed by V1DImode is MMX, about which I believe I need say nothing more, and the fact that lower-subreg produces better results than the current RA. r~
