A recent mailing list post about install.texi cleanup suggested I take a look at ours, and there were a few problems:
* No table of contents entries * Not alphabetically ordered * Missing a note about requiring binutils-2.28 gcc/ChangeLog: 2017-03-13 Palmer Dabbelt <pal...@dabbelt.com * doc/install.texi (Specific) <riscv32-*-elf>: Add table of contents link. <riscv32-*-linux>: Likewise. <riscv64-*-elf>: Likewise <riscv64-*-linux>: Likewise. <riscv64-*-elf>: Re-arrange section <riscv32-*-elf>: Add a note about requiring binutils-2.28. <riscv32-*-linux>: Likewise. <riscv64-*-elf>: Likewise <riscv64-*-linux>: Likewise. --- gcc/ChangeLog | 13 +++++++++++++ gcc/doc/install.texi | 30 +++++++++++++++++++++++------- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a4cd56f..9493330 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2017-03-13 Palmer Dabbelt <pal...@dabbelt.com + + * doc/install.texi (Specific) <riscv32-*-elf>: Add table of contents + link. + <riscv32-*-linux>: Likewise. + <riscv64-*-elf>: Likewise + <riscv64-*-linux>: Likewise. + <riscv64-*-elf>: Re-arrange section + <riscv32-*-elf>: Add a note about requiring binutils-2.28. + <riscv32-*-linux>: Likewise. + <riscv64-*-elf>: Likewise + <riscv64-*-linux>: Likewise. + 2017-03-13 Martin Liska <mli...@suse.cz> PR middle-end/78339 diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index dced17d..e7cb30c 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -3211,6 +3211,14 @@ information have to. @item @uref{#powerpcle-x-eabi,,powerpcle-*-eabi} @item +@uref{#riscv32-x-elf,,riscv32-*-elf} +@item +@uref{#riscv32-x-linux,,riscv32-*-linux} +@item +@uref{#riscv64-x-elf,,riscv64-*-elf} +@item +@uref{#riscv64-x-linux,,riscv64-*-linux} +@item @uref{#s390-x-linux,,s390-*-linux*} @item @uref{#s390x-x-linux,,s390x-*-linux*} @@ -4288,21 +4296,27 @@ This configuration is intended for embedded systems. @heading riscv32-*-elf The RISC-V RV32 instruction set. This configuration is intended for embedded systems. +This (and all other RISC-V) targets are supported upstream as of the +binutils-2.28 release. @html <hr /> @end html -@anchor{riscv64-x-elf} -@heading riscv64-*-elf -The RISC-V RV64 instruction set. -This configuration is intended for embedded systems. +@anchor{riscv32-x-linux} +@heading riscv32-*-linux +The RISC-V RV32 instruction set running GNU/Linux. +This (and all other RISC-V) targets are supported upstream as of the +binutils-2.28 release. @html <hr /> @end html -@anchor{riscv32-x-linux} -@heading riscv32-*-linux -The RISC-V RV32 instruction set running GNU/Linux. +@anchor{riscv64-x-elf} +@heading riscv64-*-elf +The RISC-V RV64 instruction set. +This configuration is intended for embedded systems. +This (and all other RISC-V) targets are supported upstream as of the +binutils-2.28 release. @html <hr /> @@ -4310,6 +4324,8 @@ The RISC-V RV32 instruction set running GNU/Linux. @anchor{riscv64-x-linux} @heading riscv64-*-linux The RISC-V RV64 instruction set running GNU/Linux. +This (and all other RISC-V) targets are supported upstream as of the +binutils-2.28 release. @html <hr /> -- 2.10.2