Hello Alexander,
In the given testcase, the generated fdivrs instruction performs the division
of a symbol ref (memory value) by FPU Stack Register and stores the value in
FPU Stack Register.
Please find the following RTL Dump of the fdivrs instruction generated. It
clearly access the memory for read access!
===============================================================================
#(insn:TI 13 20 16 2 (set (reg:XF 8 st)
# (div:XF (float_extend:XF (mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags
0x2]) [4 S4 A32]))
# (reg:XF 8 st))) {*fop_xf_4_i387}
# (nil))
fdivrs .LC0 # 13 *fop_xf_4_i387/1 [length = 6]
===============================================================================
Are we missing anything subtle here?
Regards,
Vivek Kinhekar
-----Original Message-----
From: Alexander Monakov <amona...@ispras.ru>
Sent: Friday, April 13, 2018 5:58 PM
To: Vivek Kinhekar <vivek.kinhe...@blackfigtech.com>
Cc: gcc@gcc.gnu.org
Subject: Re: GCC Compiler Optimization ignores or mistreats MFENCE memory
barrier related instruction
On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
> The mfence instruction with memory clobber asm instruction should
> create a barrier between division and printf instructions.
No, floating-point division does not touch memory, so the asm does not (and
need not) restrict its motion.
Alexander
