Hi,
DJ Delorie <[EMAIL PROTECTED]> said:
<SNIP>
> Another idea, if we can DRC fast enough, is to loop through all the
> traces and vias and increase the sizes by, say, 1/2 mil at a time each
> (if DRC allows it), re-doing until nothing more can be changed.
This sounds like a good idea, for a low speed board where the impedances are
not to be controlled. When you change the trace geometry you change the
impedance, worse yet, if you have traces with sections of different
impedances, you may get reflections at the discontinuities. This does
matter for high speed design, so we probably should not mess with trace
geometry, unless the user specifically asks for it. As for the teardrops, I
am not an expert, but they sound like a good idea to help with physical
integrity of the board. I would ask that they be a flag like the thermals,
where you have control over which vias get them. I am sure there's someone
who will not want teardrops for some reason or other...
--
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Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
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