I keep thinking about auto-teardropping pins and vias, and various
methods of doing so. On the board I just got back, with 6 mil annulii
on the vias, it's a close call for some of the drills. Also, on one
board I was reworking, the connection between the trace and annulus
broke. I was thinking, teardrops might help, but something easier
might be to just thicken the line coming out of the via - if DRC
permits it (and the lines are still small enough that there aren't any
thermal issues). Example attached, and yes, I know it only protects
one side - the other side would need more complex teardrops anyway.
The fundamental problem in any auto-teardrop system is DRC. How fast
can we DRC a tiny region of the board, or a specific line or arc?
Another idea, if we can DRC fast enough, is to loop through all the
traces and vias and increase the sizes by, say, 1/2 mil at a time each
(if DRC allows it), re-doing until nothing more can be changed.
PCB["" 45000 15000]
Grid[2500.000000 0 0 1]
Cursor[0 0 0.000000]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
Flags(0x0000000000001c40)
Groups("1,c:2,s")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,2400,2400,1200,1000:Skinny,600,2400,1200,600"]
Via[22500 2500 2400 1200 0 1200 "" ""]
Via[20000 5000 2400 1200 0 1200 "" ""]
Via[22500 7500 2400 1200 0 1200 "" ""]
Via[20000 10000 2400 1200 0 1200 "" ""]
Via[22500 12500 2400 1200 0 1200 "" ""]
Layer(1 "component")
(
Line[ 2500 2500 42500 2500 600 1200 "clearline"]
Line[42500 5000 2500 5000 600 1200 "clearline"]
Line[ 2500 7500 42500 7500 600 1200 "clearline"]
Line[42500 10000 2500 10000 600 1200 "clearline"]
Line[ 2500 12500 42500 12500 600 1200 "clearline"]
Line[22500 12500 25000 12500 2400 2000 "clearline"]
Line[20000 10000 17500 10000 2400 2000 "clearline"]
Line[22500 7500 25000 7500 2400 2000 "clearline"]
Line[20000 5000 17500 5000 2400 2000 "clearline"]
Line[22500 2500 25000 2500 2400 2000 "clearline"]
Arc[20327 4673 2173 2173 600 1200 -90 -45 "clearline"]
Arc[20327 327 2173 2173 600 1200 90 45 "clearline"]
Arc[22173 7173 2173 2173 600 1200 -90 45 "clearline"]
Arc[22173 2827 2173 2173 600 1200 90 -45 "clearline"]
Arc[20327 9673 2173 2173 600 1200 -90 -45 "clearline"]
Arc[20327 5327 2173 2173 600 1200 90 45 "clearline"]
Arc[22173 12173 2173 2173 600 1200 -90 45 "clearline"]
Arc[22173 7827 2173 2173 600 1200 90 -45 "clearline"]
Arc[20327 14673 2173 2173 600 1200 -90 -45 "clearline"]
Arc[20327 10327 2173 2173 600 1200 90 45 "clearline"]
)
Layer(2 "solder")
(
)
Layer(3 "silk")
(
)
Layer(4 "silk")
(
)
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