i see grouping of pins, not written in any syntax, but in conceptual data ignoring the concept of slots, as to include slots into pin grouping.
example of 7430 group 1 inputs A, B, C, D, E, F, G, H input-swappale = yes output Y separate data structure to map pins to footprint pingroups package = DIP example of 7401 group 1 .. 4 inputs A, B inputs-swappable = yes output Y groups-swappable = yes pingroups group 1 Package = DIP, SO pins A:2,B:3,Y:1 Package = CS // chipscale BGA i faked the pins on this one just for example pins A:a1, B:a2, Y:b1 group 2 Package = DIP, SO pins A:5,B:6,Y:4 Package = CS pins A:b2, B:c1, Y:c2 example of some FPGA with 2 8 bit ports group 0 .. 7 bus= A[0:7] bus_re-order = A:yes bus-IO-Vcc = B bus-IO-GND = C group_swappable = yes FPGA_PIN_output_script = xilinx_FPGA_pindef_gen.script // script that gets run to auto generate a pin map for this part. group 8 diff-bus=A[0:7] bus_re-order = A:yes diff-bus_pair-re-order = A:yes diff-bus_pair-P-N-swap = B:no diff-bus-clock = D bus-IO-Vcc = B bus-IO-GND = C group_swappable = yes FPGA_PIN_output_script = xilinx_FPGA_pindef_gen.script // script that gets run to auto generate a pin map for this part. imagine a fanout plugin that connects to a bus in PCB to a BGA and would choose a route that fit to the bus, thus allowing the layout decide the pin mapping :-) pingroups group 0 package = BGAfoo pins = A[0]:D1, A[1]:D2, A[2]:D3, A[4]:E2, ..., B:C2&F2, C:F3&F4&F5 group1 continued...... group 8 package = BGAfoo pins = AP[0]:Z1,AN[0]:Z2, AN[1]:........, B:......... P and N signify the diff-bus positive and negative sides of the pins This can get really hairy to implement in full but I think that it would be good. by keeping pins simple in gschem the hairiness can be kept in the external scripts used to handle these situations. the pin would have an attribute that would map it to a group say group = A or group = AP[0] just some thoughts Steve On Dec 13, 2007 2:22 PM, Dave N6NZ <[EMAIL PROTECTED]> wrote: > > > DJ Delorie wrote: > > Not directly. I've built parts with "slots" for various input pin > > permutations. > > I just realized a few days ago how that trick could be used for pin > swapping something like a two-input NAND. And then just last night I > was doing pin swapping to get better routability.... on a 32kx8 SRAM. > Let's see... 8 data lines, 15 address lines... 2^23 slots.... ummmm... > > The phrase "doesn't scale" comes to mind. > > There is a level of abstraction missing. Something like a "permutable" > attribute. So a 74as30 might have: > > permute=a:1,b:2,c:3,d:4,e:5,f:6,g:11,h:12 > > as a default, mapping pin names to pin numbers. The "net list tool" > could munge the attribute to a new mapping and then back-annotation is > simply replacing the attribute with the new mapping. gschem needs some > smarts similar to slotting to put the right pins on the schematics. > > -dave > > > > > _______________________________________________ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user