Dan McMahill wrote: > John Doty wrote: > >>> LVS is one of _layout_ verification methods. Others are DRC (often >>> separated into several checks: antenna, density etc), ERC, LVL (GDS >>> compare). >> I don't know what open source tools exist here. It would be >> interesting to investigate incorporating them into a gEDA flow. > > There is a netlist vs netlist compare tool that I started to look at. > netcmp maybe? It might have been part of magic. It is probably in the > archives for this list. > > Such a netlist vs netlist tool could actually be pretty darn useful in > doing forward/backward annotation between a board layout and schematic. > My vague memory is that the open source netlist compare tools either > weren't open source or that they had some real limitations, but my > memory of this is vague at best. > > -Dan > >
perhaps I should have googled before replying. http://opencircuitdesign.com/netgen/index.html I haven't tried it, but it looks like some work has been done to it recently. It would probably be good to teach it to deal with a better netlist format than "spice" though. Surely that is a detail that isn't too hard. -Dan _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user