On Mon, 2009-03-09 at 07:39 -0400, gene wrote: > I'm stuck. With a hierarchical design, the refdes's are long and > consuming a lot of board area. In some of the places, there just isn't > enough room place them in a meaningful way. I know this has been kicked > around before. Can anyone give me some suggestions on how to handle it?
First of all, the last board assembly house I used didn't like these refdes anyway, and insisted that I should rename everything to a flat hierarchy. Since I used blocks multiple times, and wasn't just using hierarchy to structure the design, I wasn't able to rename / backannotate that change to the schematic. Instead, I used PCB's renumber feature to spatially renumber the board (once, after placing all components), and write out a file of the changes made. I then took the file and reformated it slightly, using it as a key to feed gnetlist a renaming map. I netlist my hierarchical schematics, and the renaming map remaps the refdes to match the PCB board. (Fixing up the netlist to be correct when loaded into PCB..) I have a (simple, but hacky) patch to add this remapping functionality to gnetlist. I also had occasion to add similar functionality to PCB (again, let me know if you want the patch). This allowed me to reverse the mapping file, and un-rename the board prior to re-using it with gsch2pcb. > How small can the font be made before it becomes unreadable? Not sure.. Another technique I tried (before the above), which the assembly house didn't like, was to outline the hierarchy blocks on the board. I added manual text to those blocks labelling the hierarchy block they belonged to. Within the block, the refdes text was stripped of its hierarchy prefixes. (Again, if you want it, I have a patch to add a flag which does this to PCB). Talk to your assembler before you go ahead with either option. They both have their advantages and disadvantages. I'd say the former (the one I used) is more likely to be acceptable to the assembler, but has the down side of requiring a mapping file between the schematic refdes and PCB refdes. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user