> in general I don't like having 2 names for the same net, Maybe I'm > biased with my experience of vhdl synthesis, normally the name that you > don't expect survives synthesis and the other one gets lost (and that > even may vary between two releases of the same tool). So having only one > name has advantages.
It's not the same NET. Each NET has a name. A *BUS* is a group of nets, you can refer to the names of the nets inside it or give the bus its own name. For example: Nets A0 to A15, D0 to D7, RD, WR, and EN are grouped into a bus. You can refer to the nets within the bus when you pull them out for a connection: A[0:15],D[0:7],RD,WR,EN - all the nets A[0:1],RD,EN - some of the nets A15,D[0:7],WR,EN - some of the nets but we could also give the *grouping* a name, like "CONTROL_BUS". So, for example, you could give a bus a "netname" to enumerate the nets contained therein (just like we do for single-signal nets), as well as a "busname" to name the grouping. I can't think of a good reason to do this, but I suppose you could connect to a bus pin (aka "pin with multiple signals") and name the *bus* while leaving the individual *nets* unnamed, and carry that bus name on to a second schematic page, still without naming the nets, and connect it to another bus pin with the same number of signals, and hope it all works out :-) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user