> On May 25, 2012, 9:58 a.m., Ali Saidi wrote: > > Hi Tony, > > > > This looks pretty good. Do you have an idea how to fix the other issues? Is > > this useful enough to get some things done, or is there more to do? How > > have you tested it? I'd like to see us run some benchmarks switching back > > and forth as part of a regression test to make sure that this isn't broken > > again. > > > > Thanks agani, > > > > Ali > >
Hi Ali, I've been running BBench from boot while switching back and forth between default arm_detailed CPUs every 1,000,000 ticks. I let it run until an assert fails. Right now I can switch back and forth between O3's and will encounter a few assertion failures. I am still trying to deduce the root cause of these errors. This patch is useful in that it gets rid of some obvious bugs and allows the trickier ones to be exposed, which will hopefully get more people looking at the switchout code and how to fix it. One thing I notice is that assert(_status == IcacheWaitResponse); fails inside completeIfetch() for the simple timing cpu. The status is DcacheWaitResponse at this time and I think it's because an outstanding translation is coming back from the DTB after switchout. So, should the TLB's be drained? They currently have no drain functionality. Or should the CPU be responsible for waiting until a translation to finish before it says that it is drained? I plan to fix the other issues and to get a regression test running and committed. Thanks, Tony - Anthony ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review2804 ----------------------------------------------------------- On May 25, 2012, 9:06 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated May 25, 2012, 9:06 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9023:3c93a04acbe4 > --------------------------- > O3,ARM: This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA. This is an incremental fix as there are > still a few bugs/mem leaks with the switchout code. Particularly when > switching from an O3CPU to a TimingSimpleCPU. This patch fixes: i/d cache and > i/d TLB port re-connections when switcing out, draining of the ARM > TableWalker, and commit stage draining in the O3 CPU. > > > Diffs > ----- > > src/arch/arm/table_walker.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/arch/arm/table_walker.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/base.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/commit_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/cpu.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/iew.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/packet_queue.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
