> On May 25, 2012, 3:50 p.m., Nilay Vaish wrote: > > src/cpu/base.cc, line 388 > > <http://reviews.gem5.org/r/1221/diff/2/?file=26928#file26928line388> > > > > This will not work correctly with x86. Take a look at the line > > src/arch/x86/interrupts.cc, line 301. > > Anthony Gutierrez wrote: > Can you expound on why this is a problem? From the point of view of the > interrupt controller the CPU switchout should be transparent. Essentially the > id should remain constant regardless of which CPU model is currently active.
Because the check "cpu != NULL && cpu->cpuId() != newCPU->cpuId()" will return true and hence panic() will get triggered. Clearly cpu is not NULL. With your change, cpu and newCPU will have different Ids. This can be fixed by setting the cpuId of of the oldCPU after the interrupt controller has been. Can you explain why do you need to make this change? - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review2810 ----------------------------------------------------------- On May 25, 2012, 10:21 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated May 25, 2012, 10:21 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9023:c10d372313f0 > --------------------------- > O3,ARM: This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA. This is an incremental fix as there are > still a few bugs/mem leaks with the switchout code. Particularly when > switching from an O3CPU to a TimingSimpleCPU. This patch fixes: i/d cache and > i/d TLB port re-connections when switcing out, draining of the ARM > TableWalker, and commit stage draining in the O3 CPU. > > > Diffs > ----- > > src/arch/arm/table_walker.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/arch/arm/table_walker.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/base.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/commit_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/cpu.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/iew.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/dev/dma_device.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/packet_queue.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
