> On June 5, 2012, 11:10 a.m., Ali Saidi wrote: > > Are you still working on this? > > > > Anthony Gutierrez wrote: > Yes. I took a break to get ICS working with BBench. > > But, it switches back-and-forth between O3CPUs for a while now. My latest > problem is that while the CPU is "draining" the exit event is the next thing > scheduled. The simulator exits and the following assert fails: > cleanupCountedDrain(Event*): Assertion `event->getCount() == 0'. The only > object yet to drain is the CPU. I can send more details about the problems to > the mailing list.
Did it go negative or is it still positive? If it went negative someone thought they were drained twice. I'm not sure how it could happen that it is positive. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review2907 ----------------------------------------------------------- On May 26, 2012, 8:50 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated May 26, 2012, 8:50 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9023:bf655276f847 > --------------------------- > O3,ARM: This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA. This is an incremental fix as there are > still a few bugs/mem leaks with the switchout code. Particularly when > switching from an O3CPU to a TimingSimpleCPU. This patch fixes: i/d cache and > i/d TLB port re-connections when switcing out, draining of the ARM > TableWalker, and commit stage draining in the O3 CPU. > > > Diffs > ----- > > src/arch/arm/table_walker.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/arch/arm/table_walker.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/base.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/commit_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/cpu.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/fetch_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/cpu/o3/iew.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/dev/dma_device.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/packet_queue.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.hh bb25e7646c41469bef2b78ba435319f59d63d5fd > src/mem/port.cc bb25e7646c41469bef2b78ba435319f59d63d5fd > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
