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(Updated June 3, 2012, 8:59 a.m.) Review request for Default. Summary (updated) ----------------- ISA Parser: Allow predication of source and destination registers Description ------- Changeset 8966:c8c03cb78aa1 --------------------------- ISA Parser: Decide source register indices at runtime Currently the register indices for source and destination registers are decided statically by the isa parser. This patch moves this decision to run time. This will be useful when register will be read based on a condition specified while construction of a microop. Diffs ----- src/arch/isa_parser.py 91a6f8f07074 src/cpu/static_inst.hh 91a6f8f07074 Diff: http://reviews.gem5.org/r/1153/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
