Let me take a closer look... sorry, I've been very busy lately. Steve
On Thu, Jun 14, 2012 at 11:02 PM, Nilay Vaish <[email protected]> wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1153/#review2948 > ----------------------------------------------------------- > > > Any comments on this patch? > > - Nilay Vaish > > > On June 4, 2012, 7:35 a.m., Nilay Vaish wrote: > > > > ----------------------------------------------------------- > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.gem5.org/r/1153/ > > ----------------------------------------------------------- > > > > (Updated June 4, 2012, 7:35 a.m.) > > > > > > Review request for Default. > > > > > > Description > > ------- > > > > Changeset 9037:bf70b0132328 > > --------------------------- > > ISA Parser: Allow predication of source and destination registers > > This patch is meant for allowing predicated reads and writes. Note that > this > > predication is different from the ISA provided predication. They way we > > currently provide the ISA description for X86, we read/write registers > that > > do not need to be actually read/written. This is likely to be true for > other > > ISAs as well. This patch allows for read and write predicates to be > associated > > with operands. It allows for the register indices for source and > destination > > registers to be decided at the time when the microop is constructed. The > > run time indicies come in to play only when the at least one of the > > predicates has been provided. This patch will not affect any of the ISAs > that > > do not provide these predicates. Also the patch assumes that the order in > > which operands appear in any function of the microop is same across all > the > > functions of the microops. A subsequent patch will enable predication > for the > > x86 ISA. > > > > > > Diffs > > ----- > > > > src/arch/isa_parser.py 6385cf85bf12 > > > > Diff: http://reviews.gem5.org/r/1153/diff/ > > > > > > Testing > > ------- > > > > > > Thanks, > > > > Nilay Vaish > > > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
