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Overall, I think that trying to keep both the old model and the new model is overly complicating things. I think it's fine if all the constructors have the form: _numSrcRegs = 0; _srcRegIdx[_numSrcRegs++] = <X>; _srcRegIdx[_numSrcRegs++] = <Y>; with optional "if" clauses around the conditional registers. If there are no if clauses, then compiling with optimization should generate the same code as the old version where all the indices and values are hard coded (the compiler can do all the increments at compile time... it's just constant propagation). The python is complex enough as it is. My other concern is that all this only works if the predicate expressions evaluate the same at construction time as at execution time. I'm not sure how to enforce that, or if it's practical to do so. I can believe that that's not a problem for our current usage of this feature, but I can see that being a very subtle source of bugs in the future. src/arch/isa_parser.py <http://reviews.gem5.org/r/1153/#comment3178> Why not move the check above the padding and assignment, and then you won't have to compensate for the padding values? - Steve Reinhardt On June 4, 2012, 7:35 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1153/ > ----------------------------------------------------------- > > (Updated June 4, 2012, 7:35 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9037:bf70b0132328 > --------------------------- > ISA Parser: Allow predication of source and destination registers > This patch is meant for allowing predicated reads and writes. Note that this > predication is different from the ISA provided predication. They way we > currently provide the ISA description for X86, we read/write registers that > do not need to be actually read/written. This is likely to be true for other > ISAs as well. This patch allows for read and write predicates to be associated > with operands. It allows for the register indices for source and destination > registers to be decided at the time when the microop is constructed. The > run time indicies come in to play only when the at least one of the > predicates has been provided. This patch will not affect any of the ISAs that > do not provide these predicates. Also the patch assumes that the order in > which operands appear in any function of the microop is same across all the > functions of the microops. A subsequent patch will enable predication for the > x86 ISA. > > > Diffs > ----- > > src/arch/isa_parser.py 6385cf85bf12 > > Diff: http://reviews.gem5.org/r/1153/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
