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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1451/
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(Updated Oct. 8, 2012, 7:49 a.m.)
Review request for Default.
Summary (updated)
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Regression: Use CPU clock and 32-byte width for L1-L2 bus
Description (updated)
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changesets:
9283:4d24df0f5278 "Regression: Use CPU clock and 32-byte width for
L1-L2 bus
This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.
Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.
A separate patch will update the stats."
Diffs (updated)
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src/cpu/BaseCPU.py a5ede748a1d9
Diff: http://reviews.gem5.org/r/1451/diff/
Testing
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util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas Hansson
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