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Ship it! Ship It! - Nilay Vaish On Oct. 11, 2012, 10:05 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1451/ > ----------------------------------------------------------- > > (Updated Oct. 11, 2012, 10:05 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9284:629583c5f1d5 > --------------------------- > Regression: Use CPU clock and 32-byte width for L1-L2 bus > > This patch changes the CoherentBus between the L1s and L2 to use the > CPU clock and also four times the width compared to the default > bus. The parameters are not intending to fit every single scenario, > but rather serve as a better startingpoint than what we previously > had. > > Note that the scripts that do not use the addTwoLevelCacheHiearchy are > not affected by this change. > > A separate patch will update the stats. > > > Diffs > ----- > > configs/common/CacheConfig.py 6681c1027563 > src/cpu/BaseCPU.py 6681c1027563 > > Diff: http://reviews.gem5.org/r/1451/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
