> On Oct. 8, 2012, 6:34 a.m., Andreas Hansson wrote: > > Any objections or good to go?
I changed to 32 bytes on Ali's suggestion. This is probably on the wider side for ARM systems, and there are recent Intel systems that hit 64 bytes, but 32 should be a good starting point. Do everyone agree with the current defaults? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1451/#review3557 ----------------------------------------------------------- On Oct. 8, 2012, 7:49 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1451/ > ----------------------------------------------------------- > > (Updated Oct. 8, 2012, 7:49 a.m.) > > > Review request for Default. > > > Description > ------- > > changesets: > 9283:4d24df0f5278 "Regression: Use CPU clock and 32-byte width for > L1-L2 bus > > This patch changes the CoherentBus between the L1s and L2 to use the > CPU clock and also four times the width compared to the default > bus. The parameters are not intending to fit every single scenario, > but rather serve as a better startingpoint than what we previously > had. > > Note that the scripts that do not use the addTwoLevelCacheHiearchy are > not affected by this change. > > A separate patch will update the stats." > > > Diffs > ----- > > src/cpu/BaseCPU.py a5ede748a1d9 > > Diff: http://reviews.gem5.org/r/1451/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
