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Review request for Default. Repository: gem5 Description ------- Changeset 10022:6be85e163055 --------------------------- ruby: Add bridges between RubyPort and NoncoherentBus This patch adds bridges between the PIO port of the Ruby sequencers (based on RubyPort) and the PIO bus (based on NoncoherentBus). Both the RubyPort and the bus are multiplexing components, and as such, they should be connected by a bridge, similar to the memory bus and PIO bus in the classic memory system. The patch http://reviews.gem5.org/r/2039/ depends on this one. Diffs ----- configs/ruby/MESI_Three_Level.py a362694dda2d configs/ruby/MESI_Two_Level.py a362694dda2d configs/ruby/MI_example.py a362694dda2d configs/ruby/MOESI_CMP_directory.py a362694dda2d configs/ruby/MOESI_CMP_token.py a362694dda2d configs/ruby/MOESI_hammer.py a362694dda2d src/mem/ruby/system/RubyPort.cc a362694dda2d Diff: http://reviews.gem5.org/r/2153/diff/ Testing ------- All regressions pass (with some minor stats changes) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
