Hi Antonio, You might be able to do the same thing, but it sounds like you’re planning to run in SE mode? I’d guess that it would be about the same amount of work to make a single binary that can do both.
Ali On Jun 23, 2014, at 10:45 AM, Antonio Barbalace via gem5-dev <[email protected]> wrote: > Dear Ali, > > thank you very much for your quick feedback! > > As a gem5 beginner I do not have any better idea right now. So I think I > will start by leveraging your idea. > > I previously developed ARM + x86 in QEMU-user. With QEMU I compile one QEMU > for ARM and one for x86, then I load the QEMU-user-x86, waiting for the > connection of the QEMU-user-ARM one. At that point the execution start, I > use a special instruction to migrate both sides. Every time a VMA is > mapped, the mapping is saved in a list; during migration all the mapping > are migrated. VMAs are mapped on shared memory (i.e. between the two QEMU > processes I have shared memory). Hope this short description make sense. > > Do you think I can apply a similar approach here? > > thanks again, > Antonio > > > On Sun, Jun 22, 2014 at 12:06 PM, Ali Saidi via gem5-dev <[email protected]> > wrote: > >> Hi Antonio, >> >> Simulating ARM & x86 at the same time won’t work today. If you wanted to >> make it work, you’d need to teach the build system how to generate compile >> all the architectures into a single binary, and fix some places in the code >> where we use #defines based on the architecture to dynamically determine >> the architecture and take the appropriate action. If you end up going down >> this path, let us know, I’m sure some other people on the mailing lists >> could have suggestions. >> >> Thanks, >> Ali >> >> >> >> On Jun 21, 2014, at 6:10 PM, Antonio Barbalace via gem5-dev < >> [email protected]> wrote: >> >>> Dear all, >>> >>> I am interested in simulating heterogeneous-ISA systems, i.e. platforms >> in >>> which two or more different ISA processors (no GPUs!) coexist. E.g. ARM >> and >>> x86. >>> >>> I had a look at the following page, but is dated 2006.. >>> http://www.m5sim.org/Heterogeneous_System_Support >>> >>> Then at http://gem5.org/Projects I found MV5 and gem5-gpus. >>> Both MV5 and gem5-gpus seems to be more about CPU-GPU (well MV5 have many >>> other features about multicore). >>> >>> I finally found a Google summer of code page >>> http://m5sim.org/wiki/index.php/Google_Summer_of_Code >>> in which there is a mention about heterogeneity, focused about Cell type >>> architectures. >>> >>> I am wondering what is the current status of heterogeneous ISA support on >>> GEM5 and which is the effort needed to support heterogeneous-ISA >> processing >>> (e.g. ARM and x86)? >>> >>> many thanks, >>> Antonio >>> >>> -- >>> Dr. Eng. Antonio Barbalace, PhD >>> Systems Software Research Group (SSRG) >>> Bradley Department of Electrical and Computer Engineering >>> Virginia Tech >>> 453 Durham Hall (0111) >>> Blacksburg, VA 24061 >>> phone: +1 (540) 231-2494 >>> email: [email protected] >>> _______________________________________________ >>> gem5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/gem5-dev >>> >> >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > > > -- > Dr. Eng. Antonio Barbalace, PhD > Systems Software Research Group (SSRG) > Bradley Department of Electrical and Computer Engineering > Virginia Tech > 453 Durham Hall (0111) > Blacksburg, VA 24061 > phone: +1 (540) 231-2494 > email: [email protected] > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
