Hi Sensen,
In python you should be careful about indentation, because whitespaces are
significant in this language. This means that all lines in the same block
must start at the same indentation.
Here is an example
if A == 2:
expr1;
expr2;
expr3; ----> This is incorrect
There is one exception however: If you move some part of an expression to
the next line, you can use a different indentation for it. For example from
your own code:
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz",
trace_enable = True) -----> This is valid
system.cpu.port = system.monitor.slave
Best,
On Sun, Feb 22, 2015 at 2:19 PM, Sensen Hu - EWI via gem5-dev <
gem5-dev@gem5.org> wrote:
>
> ________________________________
> 发件人: Sensen Hu - EWI
> 发送时间: 2015年2月22日 14:06
> 收件人: gem5-dev@gem5.org
> 主题: how can I add cache in tgen-simple-mem
>
> hi, all
> I got a memory reference trace file from Pin-tools. Now I want to work out
> cache miss rate from the file.
> I use GEM5's trafficgen (TraceGen) and modified tgen-simple-mem.py by
> adding two-level cache.
> But I got a mistake diplaying by simerr.
> Could you give my some guide, thanks a lot.
>
> this is my command line:
> build/ARM/gem5.opt -d
> build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re
> --debug-flags=TrafficGen tests/run.py
> build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
>
> this is from simerr:
> Traceback (most recent call last):
> File "<string>", line 1, in <module>
> File "/home/ubuntu2e/gem5-stable/src/python/m5/main.py", line 388, in
> main
> exec filecode in scope
> File "tests/run.py", line 180, in <module>
> execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
> File "tests/configs/tgen-simple-mem.py", line 93
> cpu.clk_domain = system.cpu_clk_domain
> ^
> IndentationError: unexpected indent
>
>
>
> the following is the modified tgen-simple-mem.py file.
>
> system = System(cpu = cpu, funcmem = SimpleMemory(in_addr_map = False),
> funcbus = NoncoherentXBar(),
> physmem = SimpleMemory(),
> membus = CoherentXBar(width=16))
> # Dummy voltage domain for all our clock domains
> system.voltage_domain = VoltageDomain()
> system.clk_domain = SrcClockDomain(clock = '1GHz',
> voltage_domain = system.voltage_domain)
>
>
> #----------------------------------------------------------------------
>
> # add a communication monitor, and also trace all the packets
> system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz",
> trace_enable = True)
>
> # connect the traffic generator to the bus via a communication monitor
> system.cpu.port = system.monitor.slave
>
> #---------------------------------------------------------------------
> # Create a seperate clock domain for components that should run at
> # CPUs frequency
> system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
> voltage_domain =
> system.voltage_domain)
>
> system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16)
> system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
> assoc=8)
> system.l2c.cpu_side = system.toL2Bus.master
>
> # connect l2c to membus
> system.l2c.mem_side = system.membus.slave
>
> # add L1 caches
>
> # All cpus are associated with cpu_clk_domain
> cpu.clk_domain = system.cpu_clk_domain
> cpu.l1c = L1Cache(size = '32kB', assoc = 4)
> #cpu.l1c.cpu_side = cpu.test
> cpu.l1c.mem_side = system.toL2Bus.slave
> system.monitor.master = cpu.l1c.cpu_side
>
>
> #system.funcbus.slave = cpu.functional
>
> system.system_port = system.membus.slave
>
> # connect reference memory to funcbus
> #system.funcmem.port = system.funcbus.master
>
>
> #---------------------------------------------------------------------
>
> # connect the system port even if it is not used in this example
> system.system_port = system.membus.slave
>
> # connect memory to membus
> system.physmem.port = system.membus.master
>
>
> # -----------------------
> # run simulation
> # -----------------------
>
> root = Root(full_system = False, system = system)
> root.system.mem_mode = 'timing'
>
> _______________________________________________
> gem5-dev mailing list
> gem5-dev@gem5.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
https://www.linkedin.com/in/erfanazarkhish
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
