Dear Sensen,
If you take a look at *src/sim/ClockedObject.py*, you can see that the
parameter *clk_domain* is by default inherited from the parent. This means
that:
For all classes which are inherited from the ClockedObject class (including
CPU, memories, ...), if you do not specify any value for their clk_domain,
gem5 will automatically use the clk_domain of their parent for them.
So in your case, you do not need to assign cpu.clk_domain =
system.cpu_clk_domain. This will happen automatically. Because *system* is
the parent of the *cpu*.
But if you want to override the clock domain of on CPU explicitly and
assign it to a DIFFERENT value, you can do this:
cpu.clk_domain = SrcClockDomain(clock = '2.5GHz', voltage_domain =
VoltageDomain(voltage = '1V'))
Best,
On Tue, Feb 24, 2015 at 8:24 PM, Sensen Hu - EWI via gem5-dev <
gem5-dev@gem5.org> wrote:
> hi, Andreas.
> Thanks for your help.
> I followed your advise to delete the test.py file and just set maxtick
> directly in run.py.
> But I failed again. Could you tell me the relationship among these
> parameters
> cpu_clk_domain, system.cpu_clk_domain
>
> STATE 0 1000000 TRACE tests/quick/se/70.tgen/tgen-simple-mem.trc(the
> third data, namely 100000) and maxtick
>
>
> Could you give some advice? thank you.
>
> I attach my tgen-simple-mem.py file.
>
> import m5
> from m5.objects import *
>
> #--------------------------------------------
> m5.util.addToPath('../configs/common')
> from Caches import *
> #--------------------------------------------
>
> # both traffic generator and communication monitor are only available
> # if we have protobuf support, so potentially skip this test
> require_sim_object("TrafficGen")
> require_sim_object("CommMonitor")
>
> # even if this is only a traffic generator, call it cpu to make sure
> # the scripts are happy
> cpu = TrafficGen(config_file =
> "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
>
> # system simulated
> system = System(cpu = cpu,
> physmem = SimpleMemory(),
> membus = NoncoherentXBar(width=16))
> # Dummy voltage domain for all our clock domains
> system.voltage_domain = VoltageDomain()
> system.clk_domain = SrcClockDomain(clock = '1GHz',
> voltage_domain = system.voltage_domain)
>
>
> #----------------------------------------------------------------------
>
> # add a communication monitor, and also trace all the packets
> system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz",
> trace_enable = True)
>
> # connect the traffic generator to the bus via a communication monitor
> system.cpu.port = system.monitor.slave
>
> #---------------------------------------------------------------------
> # Create a seperate clock domain for components that should run at
> # CPUs frequency
> system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
> voltage_domain =
> system.voltage_domain)
>
> system.toL2Bus = NoncoherentXBar(clk_domain = system.cpu_clk_domain,
> width=16)
> system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
> assoc=8)
> system.l2c.cpu_side = system.toL2Bus.master
> system.l2c.mem_side = system.membus.slave
>
> cpu.clk_domain = system.cpu_clk_domain
> cpu.l1c = L1Cache(size = '16kB', assoc = 2)
>
> cpu.l1c.mem_side = system.toL2Bus.slave
> system.monitor.master = cpu.l1c.cpu_side
>
> # connect the system port even if it is not used in this example
> system.system_port = system.membus.slave
>
> # connect memory to membus
> system.physmem.port = system.membus.master
>
>
> # -----------------------
> # run simulation
> # -----------------------
>
> root = Root(full_system = False, system = system)
> root.system.mem_mode = 'timing'
> _______________________________________________
> gem5-dev mailing list
> gem5-dev@gem5.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
https://www.linkedin.com/in/erfanazarkhish
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